Soft errors from radiation particles, which are also known as single event upsets (SEU's), are a large concern in high reliability applications. In chips with even a moderate amount of unprotected static random access memory (SRAM) arrays, soft errors can dominate the error rate. Soft errors in latches are a growing concern in terrestrial applications for the 90 nm semiconductor technology and beyond. Soft errors are a greater concern in high radiation applications, such as aerospace or military applications.
Soft errors are caused by electrical charges as a radiation particle, such as an alpha particle, a charged ion, or any charged particle capable of generating electron-hole pairs as it travels through a semiconductor material such as doped wells. Electrical charges collected in such doped wells or any doped portion of a semiconductor substrate is typically dissipated through a well contact or a substrate contact. In many instances, however, the doped wells and the semiconductor substrate are configured to form parasitic bipolar transistors. Thus, when the amount of charge generated by the radiation particle within a doped well or a semiconductor substrate causes an excessive transient voltage, the parasitic transistors may turn on, causing a change in the stored data in a memory device, such as an SRAM cell.
Many known circuit techniques employed to reduce the soft error sensitivity of a circuit result in reduced areal circuit density and/or performance degradation. Fault tolerant systems can detect most or all soft errors and correct some of them, at the expense of greater complexity, and often, of performance penalties. Further, charges collected in a doped well are dissipated more rapidly as well contact spacing is reduced, thus reducing sensitivity to soft errors. However, the reduction in the well contact spacing results in a less dense circuit, i.e., a reduction in effective areal circuit density.
In general, such soft error problems are more severe in bulk substrates than in semiconductor-on-insulator (SOI) substrates. Specifically, at a given lithographic node, SOI circuits have lower soft error rates than comparable bulk circuits. The soft error rate of SOI SRAMs is often less than 20 percent of that of comparable bulk SRAMs. SOI semiconductor devices have a lower soft error rate because the volume of the semiconductor material that can collect charges generated by ionizing radiation is confined above the buried oxide (BOX). Bulk semiconductor devices have a much higher soft error rate because the volume of the semiconductor material sensitive to ionizing radiation extends at least as deep as the thickness of doped wells. In this regard, SOI substrates offer greater radiation immunity than bulk substrates. Due to the inherently higher SEU rate of devices built on a bulk substrate, the MOSFET devices built in the bulk portion of the semiconductor substrate are as prone to high soft error rates as equivalent devices built on a bulk substrate.
Therefore, there exists a need for structures for reducing soft error rates on semiconductor devices in a semiconductor substrate, and particularly in a bulk substrate, and methods of manufacturing the same.
Particularly, there exists a need for a semiconductor structure that provides reduction in voltage fluctuation during charge-generating events by a radiation particle without penalty in areal circuit density or performance, and methods of manufacturing the same.